Typical dual slope A/D converters include the cascade circuit combination of an input buffer amplifier connected to an integrator by a series resistor with the output terminal of the integrator connected to a voltage comparator. The comparator circuit generates an output indication when the integrator output potential crosses a reference level. The circuit also includes digital circuitry for stepping the A/D system through prescribed functions and generating a digital manifestation of the system input parameter being converted. Included in the digital circuitry are a system clock or oscillator and counting circuits.
In operation the dual slope converter first has the unknown parameter, e.g., a voltage to be measured, applied to the input of the buffer amplifier for a preset period. A current, I=V/R, proportional to the input voltage flows through the series resistor R and is integrated on an integrating capacitor C developing thereon a potential V.sub.I =I.DELTA.t/C where .DELTA.t is the preset period. The preset period is determined by the digital counters counting clock cycles. When the counters reach a preset count limit, the counters are reset and the unknown input potential is removed. At this point in time a reference voltage source is applied to the buffer amplifier input terminal. The reference potential, V.sub.R, is arranged to cause a reference current I.sub.R =V.sub.R /R to flow in the series resistor of opposite polarity to the preceding unknown current. The reference current is integrated on the capacitor and discharges the potential thereon. Simultaneous with the application of the reference potential to the buffer amplifier input terminal the counters are conditioned to begin counting. Counting continues until the potential on the integrating capacitor passes through the comparator trip point, typically set at zero potential. A transition of the comparator output signal stops the counters. The accumulated count in the counters is a digital representation of the value of the applied input signal.
One of the advantages of the dual slope type of converter arises from its relatively high insensitivity to temperature and other drift characteristics in the circuit components. Thus changes in the value of the resistance R or the integrating capacitance C will, to a first order, affect the charging cycle of the integrating capacitor in the same manner in which they affect the discharging cycle and hence the conversion factor between voltage and time (counts) stays constant, despite variations in the values of these circuit components. Again, provided that the bias level of the comparator is stabilized at the beginning of the charge cycle, variations in the absolute value of this level should not affect the accuracy or resolution of the conversion. While this basic circuit approach has proven very useful, some problems arise both in terms of the complexity of circuits required to provide stabilization in particular implementations of the dual slope circuit and to the use of the circuit in analog to digital converters which must have auto-polarity, that is, must respond automatically to input voltages of either polarity. These problems may arise, for example, in the complexity of circuits required to establish the comparator reference level with respect to the zero output level from the integrator.
Dual slope A/D converters are typically auto zeroed once per sample or conversion period to eliminate the effect of parameter changes, i.e., drifts, in the integrator and comparator circuits, see for example U.S. Pat. No. 3,654,560 entitled, "Drift Compensated Circuit." In the auto zero mode a feedback loop is closed around the integrator and comparator with the system input at reference potential. The closed loop unity gain output potential (offset) is established and stored on a capacitor as a reference potential for the integrating circuit. Updating circuit offsets each sample period tends to reduce system error due to such drifts or offsets thereby producing a relatively accurate conversion with relatively simple circuitry.
The accuracy of the conversion is dependent upon the circuit gain in the integrator-comparator arrangement. Very high gain is desirable in order to precisely define the comparator switching point. But for the system operating in the auto zero mode the dominant frequency pole is established by the auto zero capacitor, and the capacitance value must necessarily increase for higher values of gain to guarantee system stability. As the auto zero capacitance is increased the system response time is concomitantly increased due to the increased time necessary to establish the offset potential on the capacitor. One solution to the gain-capacitor tradeoff is to remove part of the gain stages from the auto-zero loop during auto zero operation. This allows the use of a smaller auto zero capacitor thereby decreasing the duration of the auto-zero period and thus the overall system response time.